• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    An HDR pixel comprising a photosensitive element; a detector node connected to the photosensitive element; a reset switch connected to the detector node to reset the detector node to a predetermined voltage; a buffer amplifier having an input connected to the detector node; a selection transistor for selecting said pixel during read processing; an intrinsic parasitic capacitance from the photosensitive element, or the detector node, or the reset switch, or the buffer amplifier, or the selection transistor for storing the minority carriers generated by the photosensitive element. The pixel further comprises a dual mode capacitor having an input connected to the detector node and which can be used in storage and retrieval mode, to store the minority carriers generated when it is in storage mode and to retrieve minority carriers stored in the capacitor. parasite when in destocking mode.
    公开号:BE1021668B1
    申请号:E2014/0786
    申请日:2014-10-27
    公开日:2015-12-23
    发明作者:Ward Van Der Tempel
    申请人:Softkinetic Sensors Nv；
    IPC主号:
    专利说明:

    A pixel with a large dynamic range and a method to make it work
    Technical Field of the Invention The invention relates to a high dynamic range (HDR) pixel and method for operating it. More particularly, the invention relates to an HDR pixel for performing Time-of-Flight measurements and for allowing the use of different conversion gains without destroying the load information.
    Background of the invention
    An image sensor is a device capturing and converting incident electromagnetic radiation such as a light flux into an electronic signal. In digital imaging, we mainly use active-pixel sensors (APS). APSs are image sensors consisting of an integrated circuit containing an array of pixel sensors, and wherein each pixel contains a photodiode and an active amplifier.
    In an APS, the photodiode is sensitive to incident light. Specifically, the photodiode converts the incident light into charges that are accumulated during a given exposure time and then converted into an amplified voltage in the pixel. This voltage is an analog continuous physical quantity which can be converted, by means of an analog / digital converter, into a digital value representing the amplitude of the voltage. One of the main problems of standard pixels is their potential saturation occurring when incident light becomes too strong and / or exposure, too long. In a range imaging system using Time-of-Flight (TOF) technologies, for example a Time-of-Flight 3 camera system, such as shown in FIG. 1, providing distance information by analyzing the Flying Time and the phase of a pulsed light signal 16 emitted by a controlled light source 18 and reflected by objects of the scene 15, the saturation can occur when objects having standard reflection properties are closer to the range of distance for which the imaging system 3 is calibrated. The objects then reflect the emitted light much too much and cause at least some of the pixels of the sensor to respond to their maximum value. Saturation can also occur when objects exhibit specular reflection properties in the wavelength range for which pixels have been designed to be sensitive, such as when a mirror in a scene fully reflects the incident light it receives on the sensor producing images of the scene, or when objects reflect and focus the incident light on a portion of the sensor, or when an external light source, emitting strong illumination in the same wavelength range as that for which the TOF camera has been designed, illuminates the sensor.
    When the pixels are saturated, the significant information about the scene is lost since the response provided is flattened to the maximum voltage value that can be supplied; this leads to image artifacts or defects such as burned areas, blurring effects in images. In addition, some applications, for example, computing the depth information for the TOF technology, use phase shift based computations from a plurality of shots to obtain a distance measurement. If a pixel saturation occurs during the integration time, the voltage at the detector nodes reaches a saturation threshold which alters the corresponding tap.
    Another main problem with standard pixels is that the noise can be very loud. If the signal-to-noise ratio is low, then noise is preponderant when shooting and useful information is lost.
    An important feature of an image sensor, taking into account both the saturation and noise parameters, is the so-called Dynamic Range (DR) shown in Figure 2. The Dynamic Range can be defined by the following ratio in decibels:
    For the purpose of increasing the Dynamic Range of image sensors, several techniques have been implemented. A first solution to increase the Dynamic Range of an image sensor has been to reduce the level of the background noise, for example by reducing the size of the sensors. This strategy has the disadvantage of reducing at the same time the saturation threshold of the sensor. This is the case A illustrated in Figure 2.
    Another approach to increase the Dynamic Range of the sensors is to increase the saturation threshold of the sensors. Several solutions of systems with high dynamic range (English High Dynamic range or HDR) or with very wide dynamic range (in English Wide Dynamic Range or WDR) were proposed in standard image sensors using several electronic circuits with scales and / or memory points. Sensors have been designed with techniques such as good fit, multiple shots or spatially varying exposure. In addition, an additional logic circuit has been added per APS CMOS sensor, but this reduces the effective sensor sensing area and results in a low fill factor that does not meet the efficient TOF imaging requirements. Another solution is to use circuits with logarithmic pixels. Such pixel circuits generate a voltage level which is a logarithmic function of the amount of light striking a pixel. This is different from most CMOS or CCD image sensors that use a linear type of pixel. Nevertheless, the use of logarithmic pixels greatly complicates the post-processing to compute the desired data, such as depth information for example, because it introduces well-known compression problems and also requires additional processing calculations. One of the solutions, based on increasing the saturation level, is shown in Figure 3. An additional capacitor Cpa is used, on which the charges generated during the integration time in the PD photodiode can be transferred. The main disadvantage of this method is that once transferred to the extra capacity, only one read cycle is possible. It is not possible to read the data contained in the additional capacity several times, and to adapt the conversion gain to be used.
    A solution remains to be proposed to increase the dynamic range of the Time-of-Flight sensors, while allowing multiple non-destructive readings of the same load information using different conversion gains. Summary of the invention
    The present invention relates to a high dynamic range pixel according to claim 1.
    By intrinsic capacity, it is understood that this intrinsic capacitance, which is also the parasitic capacitance Cp, is not an additional capacity added to the circuit, but is the sum of all the parasitic capacitances related to the electronic components of the circuits. that is, the sum of the capacities from at least one of the photosensitive member, the detector node, the reset switch, the buffer amplifier and the selection transistor. By definition, this intrinsic ability can not be removed alone.
    Thanks to the invention, it is also possible to choose the best conversion gain to use. Even if the loads are stored on the large capacity first, it is possible to transfer them on the parasitic capacitance, to obtain a high conversion gain.
    Preferably, the dual mode capability (Chdr) is a MOS capability that can be used to store minority carriers in reverse mode and to destock minority carriers in accumulation mode. Using a MOS capability allows for the transfer of loads in both directions, from the parasitic capacitance to the MOS capacitance and from the MOS capacitance to the parasitic capacitance. This is not possible using a standard single mode capability.
    Advantageously, the photosensitive element is an anchored photodiode allowing complete depletion of the photodiode during a charge transfer step, and thus reducing the reading noise.
    Even more advantageously, the HDR pixel is used to make Time-Of-Flight measurements. The fact of obtaining, with a single integration time, data with both a low and a high conversion gain is extremely interesting for time-of-flight measurements, since the same load information can be extracted. twice in a non-destructive way. This is advantageous for time-of-flight measurements where several correlations need to be mathematically combined to calculate the distance. The different correlations can be acquired in parallel during the same exposure or sequentially using consecutive exposures. The invention provides a way of measuring the correlations of each exposure several times using different conversion gain, without destroying the charge information.
    The present invention also relates to a method for operating a high dynamic range pixel according to claim 7.
    Advantageously, the method makes it possible to carry out measurements with a low read noise, since the resetting of the photosensitive element is carried out when the dual mode capability is in accumulation mode.
    This method is particularly advantageous for time-of-flight applications. Since multiple coherent data sets are available, there is no situation in which time-of-flight information must be computed with correlation data from different conversion gains. There is therefore no need to calibrate the different conversion gains with respect to each other, which is a very great advantage of the present invention over, for example, log-pixel, lin-log implementations. or linear by piece.
    Other advantages and new features of the invention will be better understood on reading the detailed description which follows and with reference to the accompanying drawings.
    Brief description of the drawings
    Figure 1 illustrates the basic operating principle of a TOF camera system;
    Figure 2 illustrates the definition of Large Dynamic Range;
    Figure 3 illustrates a standard pixel-3T configuration as implemented in the prior art;
    Figure 4 illustrates a pixel configuration according to one embodiment of the invention;
    Figure 5 illustrates a pixel configuration according to another embodiment of the invention;
    Figure 6 illustrates the well-known device physics of a MOS capacitor, wherein the semiconductor layer is a p-doped layer;
    Figure 7 shows the capacitive behavior of a MOS capacitor as a function of the gate voltage;
    Figure 8 is a top view of the MOS Chdr capacitor according to one embodiment of the invention;
    Figure 9 shows typical waveforms for controlling the pixel, according to one embodiment of the invention;
    Figure 10 shows an implementation of a Time-of-Flight imaging system according to an embodiment of the invention.
    Description of the invention
    Figure 4 illustrates a pixel configuration according to one embodiment of the invention.
    The pixel 40 comprises: a photosensitive element PD, for example a photodiode, for generating charges in response to a striking light; an anchored photodiode could also be used; a detector node FD, which is the node attached to the cathode of the photodiode in the case where there is no transfer gate, or a detector node FD which can be connected to the PD element by means of a transfer gate, not shown; a reset transistor Mrst responding to a control signal RTS and which can be used to initialize the photosensitive element PD at a known voltage (Vrst), or to reset the element FD to a known voltage while completely moving the anchored photodiode , if an anchored photodiode is used; an amplifier transistor MSf, for example a source follower, responding to a VDD signal and that can be used to allow the pixel voltage to be observed without removing the accumulated charge; the voltage at the detector node is transferred to the pixel output via this transistor used as an amplifier; an Msel selection transistor responding to a signal SEL and which can be used to select the pixel during a reading process; a small parasitic or intrinsic capacitance CP1 corresponding to the sum of all the parasitic capacitances of the circuit, mainly the intrinsic capacitance of the photodiode and the capacitances associated with the amplifier and reset transistors; a dual mode capability, for example a metal-oxide-semiconductor CHdr (MOS) capacitor.
    In one possible embodiment, an additional switch S2 is added to the pixel and is connected between the CMOS capacitor Chdr and the detector node FD, as shown in FIG. 5.
    The value of parasitic intrinsic capacitance CP is typically of the order of 10 fF. This small capacity makes it possible to integrate a small amount of charges, but suffers from a low saturation threshold. Its conversion gain, that is to say the ratio "voltage generated by a number of electrons generated / number of electrons generated", is high and provides high sensitivity in dark conditions.
    The MOS Chdr capacitance is made of a semiconductor or substrate body, an insulating film, a metal electrode called a gate, and one or two ohmic contacts for engaging the semiconductor body. It should be noted that a standard CMOS transistor typically comprises two ohmic regions called source and drain in contact with the semiconductor body. In the present invention, the source and the drain may be connected, as shown in Figure 4 and Figure 5, or a single zone may be designed, as in Figure 8. In the present invention, if two ohmic contacts are designed , then the MOS Chdr capacitance is arranged in such a way that the semiconductor side, ie the source and the drain of the MOS capacitor, is connected to the detection node FD of the photodetector PD.
    The conversion gain of the MOS CHDR capacity is relatively low. This large capacity is particularly useful in light conditions, since its saturation threshold is high.
    Figure 6 illustrates the well-known device physics of a MOS capacitor, in which the semiconductor layer is a p-doped layer: - If the Vg voltage applied to the gate is less than the so-called Vfb flat-band voltage, there is then a large number of holes at or near the semiconductor / oxide surface. They form an accumulation layer and the capacity is in accumulation mode. If the voltage Vg applied to the gate is greater than the so-called threshold voltage Vt, then there is an inversion layer, which is filled with inversion electrons. This is the inversion mode.
    It should be noted that the invention is presented with a p-doped MOS capacitance and that, in the following, the minority carriers are electrons, but the invention is not limited thereto and could be implemented by the those skilled in the art with n-doped capability and minority carriers being holes.
    Figure 7 shows the capacitive behavior of a Chdr MOS capacitor as a function of the gate voltage. Line (a) represents the capacitance seen on the low-frequency gate as a function of polarization conditions, while line (b) represents the capacitance seen from the semiconductor contact, doped with the same polarity as the MOS inversion layer. .
    Grid View The MOS capability has limited adaptability since at low frequency the inverting and accumulating gate capabilities are equal (Figure 7, a). However, in inversion the charges used on the other side of the capacity, that is to say on the semiconductor side, are minority carriers, while in accumulation the charges are majority carriers. This means that when we look at the minority carriers, that is to say the minority carriers integrated during the integration time by the PD photodiode, no charge can accumulate in the accumulation capacity. This means that, for minority carriers, there is no capacity when the MOS capacity is accumulating (Figure 7, b).
    When the gate voltage of the structure of FIG. 4 or FIG. 5 corresponds to the inversion mode of the capacitance, the capacitance can now accept minority carriers of the semiconductor contact and can act as a capacitance for these charges, in this case electrons. When the gate voltage corresponds to the accumulation mode, the minority carriers that were present in the channel are now pushed into the semiconductor region again, which alters the capacity on that node without changing the charge information. In this way, it is possible to switch between a mode with a high capacity for the minority carriers and a low conversion gain (MOS in inversion) and a mode with a low capacity and a high conversion gain (MOS in accumulation). The use of the dual mode MOS Chdr capacitor enables the transfer of charges: from the parasitic capacitance CP to the large capacitor Chdr by opening the switch S2 and applying a gate voltage Vg such that the capacitor CHdr is used in inversion, and in such a way that the total capacity seen by the minority carriers is the sum of Cp and Chdr! and from the large capacitance CHdr to the parasitic capacitance Cp by applying a gate voltage Vg such that the capacitor Chdr is used in accumulation mode and pushes the minority carriers towards the parasitic capacitance, so that the total capacitance CT seen by the Minority carriers is only CP.
    Pixel 40 of the present invention, including this dual-mode MOS capability, is of particular interest in a Time-of-Flight camera system. Preferably, the pixel 40 of the present invention can be used to perform Time-of-Flight measurements. The pixel 40 may be, for example, a pixel of a Current-Assisted Photonic Demodulator (CAPD) for performing Time-of-Flight correlation measurements, but the invention is not not limited to that. Due to the dual mode MOS capability, the same charge information can be extracted twice non-destructively, which is advantageous for Time-of-Flight measurements where several correlations must be mathematically combined to calculate the distance. The different correlations can be acquired in parallel during the same exposure or sequentially using consecutive exposures. The invention provides a way to measure the correlations of each exposure multiple times using different conversion gains without destroying the load information. This is important for Time-of-Flight since, in order to mathematically combine the correlation data, the correlation data set must be consistent and measured using the same conversion gain. Now, with the present invention, multiple sets of data are available and consistent. Each correlation data point in a set is measured using the same conversion gain, and several sets are available, in which the sets are measured with different conversion gains. This means that for low intensity measurements, when the collected load is low, the data set with a high conversion gain can be used (ie parasitic capacitance Cp), whereas for measurements At high intensity, the low conversion gain data set can be used (ie the MOS Chdr capability), since the information, when measured with a high conversion gain, will have saturated.
    A view from above of the Chdr MOS capacitor is provided in FIG. 8. The region 72 is a top view of the CMOS capacitance grid, under which the insulator and semiconductor layers are located. Region 71 is an ohmic contact in contact with the semiconductor layer, to allow minority carriers to enter and exit the MOS capacitor. In FIG. 8, only one ohmic contact 71 is shown, but the invention could include two ohmic contacts. It should be noted that a standard CMOS transistor typically comprises two ohmic contacts called source and drain. In the present invention, the source and the drain may be connected, as shown in Figure 4 and Figure 5, or only one zone may be designed, as in Figure 8. Only one ohmic contact is required to allow carriers minority to enter and exit the MOS capacity.
    The value of the additional capacity Chdr that can be activated or deactivated is proportional to the grid capacity per unit, typically of the order of 4 fF / pm 2, is proportional to the width of the MOS 75 capacity and to the length of the capacitance MOS 74. However, the addition of the structure also adds a parasitic capacitance which is proportional to the width 75, to the contact length 73 - which depends on the technology and must be minimized - and to the junction capacity of that region active 71, also dependent on technology. In order to have a high modulation of the capacitance at the FD node, it is necessary to minimize the parasitic capacitance CP (which can not be deactivated) by minimizing the width of the MOS structure 75 and maximizing the length of the MOS structure 74. Ratios Modulation from 6: 1 to 10: 1 can be achieved by optimizing the length and width 74 and 75, respectively, providing an improvement in the dynamic range of up to 20dB. Other more exotic implementations of the MOS structure are also possible, such as a single drain / source contact surrounded by a circular grid, and so on.
    Figure 9 shows typical waveforms for controlling the pixel, illustrating the method of the invention.
    At time T1, the source follower Msf is reset to the value VDD.
    Then, a reset pulse is given to the transistor gate Mrst until time T2. During the reset, the MOS Chdr capacity is left in accumulation, with a low Vhdr, which means that for the minority carriers there is only the parasitic capacitance Cp. Therefore, the kTC noise created by the reset is defined only by the parasitic capacitance CP, being the sum of the parasitic capacitance of the detection diode PD in parallel with the remaining parasitic capacitance on the FD node (for example the capacitance d MSF amplifier input)
    After the reset, the MOS is biased at low inversion, at time T3, and the integration time begins. For any charge accumulated on the node FD, the additional capacity Chdr will be seen, the integration of the charge information therefore takes place during the exposure on the total capacity Ct being the sum of Cp and Chdr ·
    At time T4, the exposure time is over and the information is sampled. Load information is read on the total capacity Cr, which means that a low conversion gain is used.
    After this first read operation, the capacitance MOS Chdr is switched into accumulation (or at least in flat band) with a low Vhdr threshold, between the times T5 and T6, and the minority carriers present previously in the inversion layer are pushed back into the semiconductor contact 71 connected to the node FD. Preferably, the times T5 and T6 are chosen such that the change between the inversion and accumulation modes is slow and not abrupt, to ensure better charge transfer. Times T5 and T6 could also be merged in one time. The same information load can then be read on the low capacitance Cp, which means that a high conversion gain is used during this second read operation.
    If the data read in this high conversion gain mode is saturated, then Time-of-Flight calculations can be made using the data acquired in the low conversion gain mode, at time T3, and a choice can be made. made.
    In one embodiment, when a switch S2 is used, as shown in Figure 5, then the switch can be kept closed until time T4 (signal TW). Then, the switch can be opened to allow full charge transfer during the first read step. The invention can also be used in a global shutter pixel approach by implementing a transfer gate between the PD element and the FD element. The dual mode capability is reconnected to the FD element.
    For the case where the PD element is not an anchored photodiode, when the transfer gate is conducting, the collected carriers are distributed between PD and FD to have an equal potential on the two nodes. It is therefore advantageous to have a large capacity on FD, so that the majority of carriers collected will be stored on the FD side. When the transfer gate is released, the situation is blocked.
    Now, the electrons on the FD node can be read first in low conversion gain mode and then in high conversion gain mode by bringing the MOS structure back into accumulation. In doing so, a better charge transfer is obtained from PD to FD compared to a normal global shutter mode. The amount of charges lost is without the dual mode capability (Cpd / (Cpd + CFd)) which typically approaches У g, whereas in the present invention the amount of charges lost in the overall shutter operation is reduced to (CPD / (Cpd + Cfd + Chdr)) while maintaining approximately the original FD conversion gain in high conversion gain mode.
    Figure 10 shows an implementation of a Time-of-Flight 900 imaging system using the dynamic range enhancement of the invention. A pixel array 901, comprising a pixel array 40 according to any of the embodiments of this invention, is connected to a read module 902 which may be an ADC, an analog output buffer, a set of ADCs in parallel etc, and a synchronization module 902 for reading each pixel in multiple modes.
    权利要求:
    Claims (7)
    [1]
    A high dynamic range (HDR) pixel (40) operable to perform flight time measurements comprising: - a photosensitive element (PD) for generating majority and minority carriers in response to incident radiation during a flight time measurement; integration time; a detector node (FD) connected to the photosensitive element (PD); a reset switch (MRSt) connected to the detector node (FD) for resetting the detector node (FD) to a predetermined voltage; a buffer amplifier (MSf) having an input connected to the detector node (FD); a selection transistor (MSE1). operable to select said pixel during read processing; an intrinsic parasitic capacitance (Cp) originating from at least one of the photosensitive element (PD), the detector node (FD), the reset switch (Mrst), the buffer amplifier (MSf), selecting transistor (MSel) and can be used to store the minority carriers generated by the photosensitive element (PD); characterized in that the pixel (40) further comprises: - a dual mode capacitance (Chdr) having an input connected to the detector node (FD) and operable in storage and retrieval mode, for storing the minority carriers generated when it is in storage mode and destock the minority carriers stored in the parasitic capacitance when it is in destocking mode; and the pixel (40) operable to perform flight time measurements by selecting a low conversion gain or a high conversion gain and processing pixel data corresponding to the minority carriers stored on the sum of the parasitic capacitance (CP ) and dual mode capacity (CHDR), in the case of a small conversion gain, or corresponding to the minority holders stored only on the parasitic capacitance (CP), in case of a high conversion gain.
    [2]
    2. The LREPIXEL HDR (4Q) of claim 1, wherein the dual mode capability (CHdr) is a MOS capability that can be used to store minority carriers in reverse mode and to destock minority carriers in accumulation mode.
    [3]
    The HDR pixel (40) of claim 1 or 2, wherein the photodiode is an anchored photodiode.
    [4]
    4. The HDR pixel (40) The HDR pixel (40) according to any one of the preceding claims, further comprising a transfer gate connected between the photosensitive member (PD) and the detector node (FD).
    [5]
    A time-of-flight imaging system (900) comprising an HDR pixel array (901) (40) according to any one of the preceding claims, and further comprising a read module (902) for reading the pixel data and a synchronization module (903) for controlling both the pixel array (901) and the read module (902).
    [6]
    A method for operating the HDR pixel (40) to perform flight time measurements according to any one of the preceding claims, the method comprising the steps of: - resetting the photosensitive element (PD) while maintaining the dual mode capability (Chdr) in destocking mode; - integrating loads in response to incident radiation while maintaining the dual mode capability (CHdr) in storage mode, to store minority carriers on both parasitic capacitance (CP) and dual mode capability (Chdr); - read pixel data corresponding to the minority carriers stored on both parasitic capacitance (CP) and dual mode capability (Chdr); - switch the dual mode capability (Chdr) in destocking mode to destock the minority carriers in the parasitic capacitance (CP); - read pixel data corresponding to the minority carriers stored on parasitic capacitance (CP) only.
    [7]
    7. The method of claim 6, wherein the step of switching the dual mode capability (CHdr) in destocking mode is not performed abruptly.
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    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    EP14176159.3A|EP2966856B1|2014-07-08|2014-07-08|A high dynamic range pixel and a method for operating it|
    EP141761593|2014-07-08|
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